The caching invalidation guidelines from the AMD-Vi specification (48882—Rev
3.07-PUB—Oct 2022) is incorrect on some hardware, as devices will malfunction
(see stale DMA mappings) if some fields of the DTE are updated but the IOMMU
TLB is not flushed.
Such stale DMA mappings can point to memory ranges not owned by the guest, thus
allowing access to unindented memory regions.
References
Link | Resource |
---|---|
https://xenbits.xenproject.org/xsa/advisory-442.html | Vendor Advisory |
https://xenbits.xenproject.org/xsa/advisory-442.html | Vendor Advisory |
Configurations
History
21 Nov 2024, 08:07
Type | Values Removed | Values Added |
---|---|---|
References | () https://xenbits.xenproject.org/xsa/advisory-442.html - Vendor Advisory |
11 Jan 2024, 15:57
Type | Values Removed | Values Added |
---|---|---|
References | () https://xenbits.xenproject.org/xsa/advisory-442.html - Vendor Advisory | |
CPE | cpe:2.3:o:xen:xen:*:*:*:*:*:*:*:* | |
First Time |
Xen
Xen xen |
|
CWE | NVD-CWE-noinfo | |
CVSS |
v2 : v3 : |
v2 : unknown
v3 : 7.8 |
05 Jan 2024, 18:23
Type | Values Removed | Values Added |
---|---|---|
New CVE |
Information
Published : 2024-01-05 17:15
Updated : 2024-11-21 08:07
NVD link : CVE-2023-34326
Mitre link : CVE-2023-34326
CVE.ORG link : CVE-2023-34326
JSON object : View
Products Affected
xen
- xen
CWE